This is the first post in a series about RISC-V, an open-source processor architecture. In this post, the architecture will be introduced and a brief summary of its history will be discussed, while future posts will expand upon the processor's design, some general problems with RISC-V, and how users can contribute to the project. Additionally, because this post is more academic in nature than previous posts, it will also include citations for readers to follow for more information.
What is RISC-V?
RISC-V, pronounced "risk five", is a processor architecture created at the University of California, Berkeley in 2010. It was created when two research projects using other architectures completed and researchers wanted an open architecture that they could modify and implement based on their own designs and research.[1] At the time, several other architectures were considered and rejected for one reason or another - limitations in the designs themselves were one common reason, while proprietary standards that prevented modifications were another. Eventually all other options were exhausted and thus the RISC-V instruction set architecture was born.
Of course, a low-level design like that is difficult to produce, and even after it has been created it's useless without an implementation. After 4 years of work, the RISC-V designers finally finished the user-level instruction set and were able to begin work on implementing it. In 2015, a team at Berkeley created the Berkeley Out-of-Order Machine (BOOM) based on RISC-V.[2] This was designed using Chisel, a hardware design language also created at Berkeley, and implemented using Rocket-Chip, a generator for SoCs that was yet again a product of research at Berkeley. As a result of the close coordination, the first version of BOOM was able to come close to matching the ARM Cortex-A15 processor from 2011, which is no small feat for a processor that was barely a concept in 2011. In 2017, BOOMv2 was created with improvements to instruction fetching, issue windows, and memory registers.[3] While benchmarks were not provided, adding features like branch prediction is generally a huge improvement to a processor's capabilities, although there were tradeoffs between Instructions Per Cycle (IPC) and core clock frequencies.
Outside Berkeley
If U.C., Berkeley was the only place where RISC-V was used, the project would never have the impact that it potentially does today. Luckily, that isn't the case and researchers at other universities have caught on. Berkeley's sister campus in Davis, California also created a RISC-V design using Chisel, but theirs is more oriented toward teaching.[4] DINO (Davis In-Order CPU) is the result of that effort, mainly aimed at teaching senior-level students the basics of CPU design. This has resulted in a toolchain that is easy for instructors to set up, allowing for even first-time instructors with computer architecture experience to pick up the class assignments, solve them, and modify them with relative ease. Additionally, because of RISC-V's open-source nature, researchers at U.C. Davis are able to push their improvements back to the central design repository, leading to overall improvements for everyone.
RISC-V has also expanded outside of the United States, gathering research contributions from around the globe. Researchers from the Indian Institute of Technology, Madras created SHAKTI-MS, a processor designed for secure programming using the RISC-V design.[5] The goal of their processor was to create a system that would detect and stop misused pointers in compiled C and C++ programs, thus preventing security vulnerabilities such as buffer overflows. Meanwhile, international researchers from both Seoul National University and the University of Cambridge developed a method to improve concurrent processing for both ARM and RISC-V processors.[6] Given the recent advancements in processor core counts thanks to AMD's Ryzen processors, concurrent programming is becoming more common so this is a big step toward RISC-V becoming a viable processor option outside of academia. Small incremental steps like these are the lifeblood of an open-source project, and RISC-V is steadily gaining momentum as more contributions are made.
Slow and steady growth
RISC-V may not be competitive with x86 currently, but it spent the first 4-5 years of its life as an academic project. Since then, computer engineers worldwide have had the opportunity to implement their own version based on what they want or need, all for free. Additionally, companies like Google and Samsung have funded the RISC-V project to help accelerate growth, which means we are sure to see more of it in the future.
References
[1] Waterman, Andrew Shell. “Design of the RISC-V Instruction Set Architecture.” UC Berkeley, 2016. https://escholarship.org/uc/item/7zj0b3m7#main.
[2] Celio, Christopher, David A. Patterson, and Krste Asanović. “The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor | EECS at UC Berkeley.” Accessed October 27, 2019. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-167.html.
[3] Celio, Christopher, Pi-Feng Chiu, Borivoje Nikolic, David A Patterson, and Krste Asanović. “BOOM v2: An Open-Source out-of-Order RISC-V Core | EECS at UC Berkeley.” Accessed October 27, 2019. https://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-157.html.
[4] Lowe-Power, Jason, and Christopher Nitta. “The Davis In-Order (DINO) CPU: A Teaching-Focused RISC-V CPU Design.” In Proceedings of the Workshop on Computer Architecture Education, 2:1–2:8. WCAE’19. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3338698.3338892.
[5] Das, Sourav, R. Harikrishnan Unnithan, Arjun Menon, Chester Rebeiro, and Kamakoti Veezhinathan. “SHAKTI-MS: A RISC-V Processor for Memory Safety in C.” In Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, 19–32. LCTES 2019. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3316482.3326356.
[6] Pulte, Christopher, Jean Pichon-Pharabod, Jeehoon Kang, Sung-Hwan Lee, and Chung-Kil Hur. “Promising-ARM/RISC-V: A Simpler and Faster Operational Concurrency Model.” In Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 1–15. PLDI 2019. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3314221.3314624.
[7] https://riscv.org/members-at-a-glance/